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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
User’s Manual U15905EJ2V1UD
226
(4) Compare operation
The TMn register has two capture/compare registers. These are the CCn0 register and the CCn1 register. A
capture operation or a compare operation is performed according to the settings of both the CMSn1 and
CMSn0 bits of the TMCn1 register. If the CMSn1 and CMSn0 bits of the TMCn1 register are set to 1, the
register operates as a compare register.
A compare operation that compares the value that was set in the compare register and the TMn register count
value is performed.
If the TMn register count value matches the value of the compare register, which had been set in advance, a
match signal is sent to the output controller. The match signal causes the timer output pin (TOn) to change
and an interrupt request signal (INTCCnn) to be generated at the same time.
If the CCn0 or CCn1 registers are set to 0000H, the 0000H after the TMn register counts up from FFFFH to
0000H is judged as a match. In this case, the TMn register value is cleared (0) at the next count timing,
however, this 0000H is not judged as a match. Also, the 0000H when the TMn register begins counting is not
judged as a match.
If match clearing is enabled (CCLRn bit = 1) for the CCn0 register, the TMn register is cleared when a match
with the TMn register occurs during a compare operation.
Remark
n = 0, 1
Figure 7-6. Compare Operation Example (When CCLR1 = 1 and CC10 Is Other Than 0000H)
0001H
0000H
n
1
TM1
Compare register
(CC10)
Match detection
(INTCC10)
Remarks 1. A match is detected immediately after the count-up, and the match detection signal is generated.
2. n
≠ 0000H
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